To complicate matters further, the materials used in chip layouts and their pre-manufacture simulations are treated as if they provide an “ideal” connection between different layers of a device. However, that “ideal” state isn’t matched in reality. In fact, many chip layouts contain unwanted parasitic resistance, induction and capacitance points that are created through the interplay of the densely sandwiched layers that make up a chip. These parasitic nodes can wreak havoc on the performance of a chip and, therefore, must be extracted from a design before it’s sent off for manufacture. 

But how does a layout designer detect these parasitic points on chip design? In this 10-page white paper, you will learn about a platform integration which provides designers with a fast, highly accurate, and multi-purpose parasitic extraction tool that enables post-layout simulation across a wide range of designs and advanced process nodes.